How to: multidimensional arrays in vhdl -

How to: multidimensional arrays in vhdl -

i'm trying create 5 dimensional array in vhdl i'm unsure how set , initialize bits.

here have far:

type \1-line\ array (4 - 1 downto 0) of unsigned (32 - 1 downto 0); type square array (4 - 1 downto 0) of \1-line\; type cube array (4 - 1 downto 0) of square; type hypercube array (4 - 1 downto 0) of cube; type \5-cube\ array (4 - 1 downto 0) of cube; signal mega_array : \5-cube\; begin process (clock, reset) begin if (reset == '1') mega_array <= '0'; end if; end process; end behv;

a way '(others =>'0')'. clean , safe way set bits of vector @ '0'. have every layer of array.

library ieee; utilize ieee.std_logic_1164.all; utilize ieee.numeric_std.all; entity test port ( clock : in std_logic; reset : in std_logic); end entity test; architecture behv of test type \1-line\ array (4 - 1 downto 0) of unsigned (32 - 1 downto 0); type square array (4 - 1 downto 0) of \1-line\; type cube array (4 - 1 downto 0) of square; type \5-cube\ array (4 - 1 downto 0) of cube; signal mega_array : \5-cube\; begin process (clock, reset) begin if (reset = '1') -- note: not '==' mega_array <= (others => (others => (others => (others => (others => '0'))))); end if; end process; end architecture behv;

note although \1-... naming right vhdl, not utilize avoid nasty tools issues. i'm not sure come, avoiding them improve solving them. utilize t_1line instead.

arrays vhdl