verilog array referencing -

verilog array referencing -

i have module. question gamearray[0][x][y-1] doesn't work. right way perform kind of operation? similar c++ syntax can not work.

module write_init_copy( input clk, input gamearray [1:0][63:0][127:0], writecell, processedcell, input [5:0] x, input [6:0] y, input initialize, copyover, output reg done_initialize, done_copy, done_writecell); always@(posedge clk) begin if(writecell == 1) begin gamearray[1][x][y] <= processedcell; done_writecell <= 1; end else if(initialize == 1) begin end end endmodule

gamearray declared input can't assign it. if want want modify declare separate 'in' , 'out' version out <= f(in); i.e.

gamearray_out <= gamearray_in; gamearray_out[1][x][y] <= procesedcell;

verilog