Is there a way to reference a target specific variable in a Makefile's Rule? -

Is there a way to reference a target specific variable in a Makefile's Rule? -

1 target foo : src = foo.c 2 target foo : obj = foo.o 3 target bar : src = bar.c 4 target bar : obj = bar.o 5 foo bar: obj # problem - not recognizing obj! 6 @echo link ${bin} 7 @gcc command link ${obj} 8 foo.o bar.o 9 @echo compile ${src} 10 @gcc command compile ${src}

so, target specific variable great target recipe used in lines 6,7,9 & 10. however, there way can reference target specific variable "obj" in target rule have in line 5? i'm thinking there is, need voodoo symbol reference it. can't believe couldn't find reply anywhere. in advance!

use secondary expansion:

.secondexpansion: foo bar: $$(obj) ...

makefile target