vhd - std_logic_vector vs. integer synthesis in Xilinx vhdl -

vhd - std_logic_vector vs. integer synthesis in Xilinx vhdl -

i working in 8 bit pixel values..for ease of coding want utilize conv_integer convert 8 bit std_logic_vector.is cause synthesise problem?is cut down speed of hardware...

no, integers synthesise fine. don't utilize conv_integer though - that's old non-standard library.

you want use ieee.numeric_std; , to_integer(unsigned(some_vector));

if still want access bits, , treat vector number, utilize signed or unsigned type - define vectors of bits (which can still have -, z etc.) behave numbers, can write unsigned_vector <= unsigned_vector + 1.

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