x86 - Interconnect between per-core L2 and L3 in Core i7 -

x86 - Interconnect between per-core L2 and L3 in Core i7 -

the intel core i7 has per-core l1 , l2 caches, , big shared l3 cache. need know kind of interconnect connects multiple l2s single l3. student, , need write rough behavioral model of cache subsystem. crossbar? single bus? ring? references came across mention structural details of caches, none of them mention kind of on-chip interconnect exists.

thanks,

-neha

modern i7's utilize ring. tom's hardware:

earlier year, had chance talk sailesh kottapalli, senior principle engineer @ intel, explained he’d seen sustained bandwidth close 300 gb/s xeon 7500-series’ llc, enabled ring bus. additionally, intel confirmed @ idf every 1 of products in development employs ring bus.

your model rough, may able glean more info public info on i7 performance counters pertaining l3.

x86 computer-architecture cpu-cache